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DATASHEET
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Description
ICS9FG108 is a Frequency Timing Generator that provides 8 differential output pairs that are compliant to the Intel CK410 specification. It also provides support for PCI-Express, next generation I/O, and SATA. The part synthesizes several output frequencies from either a 14.31818 Mhz crystal or a 25 MHz crystal. The device can also be driven by a reference input clock instead of a crystal. It provides outputs with cycle-to-cycle jitter of less than 50 ps and output-to-output skew of less than 65 ps. ICS9FG108 also provides a copy of the reference clock. Frequency selection can be accomplished via strap pins or SMBus control.
ICS9FG108
Features/Benefits
* * * * * * * * Generates common frequencies from 14.318 MHz or 25 MHz Crystal or reference input 8 - 0.7V current-mode differential output pairs Supports Serial-ATA at 100 MHz Two spread spectrum modes: 0 to -0.5 downspread and +/-0.25% centerspread Unused inputs may be disabled in either driven or Hi-Z state for power management. Programmable OE Polarity M/N Programming
Key Specifications
* * * * * * Output cycle-to-cycle jitter < 50 ps Output to output skew < 65 ps +/-300 ppm frequency accuracy on output clocks +/-150 ppm frequency accuracy @100 MHz outputs 48-pin SSOP/TSSOP package Available in RoHS compliant packaging
Funtional Block Diagram
XIN/CLKIN OSC X2 OE(7:0)
R EFO U T
PROGRAMMABLE SPREAD PLL
STOP LOGIC
8 DIF(7:0)
SPREAD SEL14M_25M# DIF_STOP# FS(2:0) SDATA SCLK CONTROL LOGIC
IREF
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G
04/06/07
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ICS9FG108 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Pin Configuration
XIN/CLKIN X2 VDD GND REFOUT **FS2 **OE_7 DIF_7 DIF_7# VDD DIF_6 DIF_6# *OE_6 VDD GND *OE_5 DIF_5 DIF_5# VDD DIF_4 DIF_4# **OE_4 SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDA GNDA IREF **FS0 **FS1 **OE_0 DIF_0 DIF_0# VDD DIF_1 DIF_1# *OE_1 VDD GND *OE_2 DIF_2 DIF_2# VDD DIF_3 DIF_3# **OE_3 *SEL14M_25M# **SPREAD DIF_STOP#
Functionality Table
Frequency Select Table SEL14M_25M# FS2 FS1 FS0 OUTPUT(MHz) (FS3) 0 0 0 0 100.00 0 0 0 1 125.00 0 0 1 0 133.33 0 0 1 1 166.67 0 1 0 0 200.00 0 1 0 1 266.66 0 1 1 0 333.33 0 1 1 1 400.00 1 0 0 0 100.00 1 0 0 1 125.00 1 0 1 0 133.33 1 0 1 1 166.67 1 1 0 0 200.00 1 1 0 1 266.66 1 1 1 0 333.33 1 1 1 1 400.00
* indicates internal 120K pull up ** indicates internal 120K pull down
48-pin SSOP & TSSOP
Power Groups
Pin Number VDD GND 3 4 10,14,19,31,36,40 15,35 N/A 47 48 47 Description REFOUT, Digital Inputs, SMBus DIF Outputs IREF Analog VDD & GND for PLL Core
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
ICS9FG108
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ICS9FG108 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Pin Description
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN NAME XIN/CLKIN X2 VDD GND REFOUT **FS2 **OE_7 DIF_7 DIF_7# VDD DIF_6 DIF_6# *OE_6 VDD GND *OE_5 DIF_5 DIF_5# VDD DIF_4 DIF_4# **OE_4 SDATA SCLK PIN TYPE IN OUT PWR PWR OUT IN IN OUT OUT PWR OUT OUT IN PWR PWR IN OUT OUT PWR OUT OUT IN I/O IN DESCRIPTION Crystal input or Reference Clock input Crystal output, Nominally 14.318MHz Power supply, nominal 3.3V Ground pin. Reference Clock output Frequency select pin. Active high input for enabling output 7. 0 = tri-state outputs, 1= enable outputs 0.7V differential true clock output 0.7V differential complement clock output Power supply, nominal 3.3V 0.7V differential true clock output 0.7V differential complement clock output Active high input for enabling output 6. 0 = tri-state outputs, 1= enable outputs Power supply, nominal 3.3V Ground pin. Active high input for enabling output 5. 0 = tri-state outputs, 1= enable outputs 0.7V differential true clock output 0.7V differential complement clock output Power supply, nominal 3.3V 0.7V differential true clock output 0.7V differential complement clock output Active high input for enabling output 4. 0 = tri-state outputs, 1= enable outputs Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant.
Note: Pin names followed by '**' have 120 Kohm pull DOWN resistors Pin names followed by '*' have 120 Kohm pull UP resistors
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
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ICS9FG108 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Pin Description (continued)
PIN # 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Note: PIN NAME DIF_STOP# **SPREAD *SEL14M_25M# **OE_3 DIF_3# DIF_3 VDD DIF_2# DIF_2 *OE_2 GND VDD *OE_1 DIF_1# DIF_1 VDD DIF_0# DIF_0 **OE_0 **FS1 **FS0 IREF GNDA VDDA PIN TYPE IN IN IN IN OUT OUT PWR OUT OUT IN PWR PWR IN OUT OUT PWR OUT OUT IN I/O IN OUT PWR PWR DESCRIPTION Active low input to stop differential output clocks. Asynchronous, active high input to enable spread spectrum functionality. Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz, 0 = 25 MHz Active high input for enabling output 3. 0 = tri-state outputs, 1= enable outputs 0.7V differential complement clock output 0.7V differential true clock output Power supply, nominal 3.3V 0.7V differential complement clock output 0.7V differential true clock output Active high input for enabling output 2. 0 = tri-state outputs, 1= enable outputs Ground pin. Power supply, nominal 3.3V Active high input for enabling output 1. 0 = tri-state outputs, 1= enable outputs 0.7V differential complement clock output 0.7V differential true clock output Power supply, nominal 3.3V 0.7V differential complement clock output 0.7V differential true clock output Active high input for enabling output 0. 0 = tri-state outputs, 1= enable outputs Frequency select latch input pin / 3.3V 66.66MHz clock output. 3.3V Frequency select latched input pin. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core.
Pin names followed by '**' have 120 Kohm pull DOWN resistors Pin names followed by '*' have 120 Kohm pull UP resistors
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
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ICS9FG108 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
General SMBus serial interface information for the ICS9FG108 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address DC (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address DC (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address DD (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address DC(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address DC(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address DD(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Not acknowledge stoP bit
ICS9FG108 REV G 04/06/07
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ICS9FG108 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD) Pin # Name Control Function Type Byte 0 1 SEL14M_25M# 27 RW Bit 7 (FS3) 6 RW Bit 6 FS21 RW 44 Bit 5 FS11 RW 45 Bit 4 FS01 1 26 RW Bit 3 Spread Enable Enable Software Control of Frequency, Spread RW Bit 2 Enable (Spread Type always Software Control) RW DIF_STOP# drive mode Bit 1 RW Spread Type Bit 0
0
1
PWD Pin 27
See Frequency Selection Table, Page 1
Off Hardware Select Driven Down
On Software Select Hi-Z Center
Pin 6 Pin 44 Pin 45 Pin 26 0 0 0
Notes: 1. These bits reflect the state of the corresponding pins at power up, but may be written to if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin. SMBus Table: Output Enable Register Pin # Name Byte 1 DIF_7 EN Bit 7 DIF_6 EN Bit 6 DIF_5 EN Bit 5 DIF_4 EN Bit 4 DIF_3 EN Bit 3 DIF_2 EN Bit 2 DIF_1 EN Bit 1 DIF_0 EN Bit 0 SMBus Table: Output Stop Mode Register Byte 2 Name Pin # DIF_7 STOP EN Bit 7 DIF_6 STOP EN Bit 6 DIF_5 STOP EN Bit 5 DIF_4 STOP EN Bit 4 DIF_3 STOP EN Bit 3 DIF_2 STOP EN Bit 2 DIF_1 STOP EN Bit 1 DIF_0 STOP EN Bit 0
Control Function Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable
Type RW RW RW RW RW RW RW RW
0 Disable Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Enable Enable Enable Enable Enable Enable
PWD 1 1 1 1 1 1 1 1
Control Function Free Run/ Stop Enable Free Run/ Stop Enable Free Run/ Stop Enable Free Run/ Stop Enable Free Run/ Stop Enable Free Run/ Stop Enable Free Run/ Stop Enable Free Run/ Stop Enable
Type RW RW RW RW RW RW RW RW
0 Free-run Free-run Free-run Free-run Free-run Free-run Free-run Free-run
1 Stop-able Stop-able Stop-able Stop-able Stop-able Stop-able Stop-able Stop-able
PWD 0 0 0 0 0 0 0 0
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
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ICS9FG108 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: Frequency Select Readback Register Pin # Name Control Function Byte 3 1 SEL14M_25M# 27 State of pin 27 Bit 7 (FS3) 6 State of pin 6 Bit 6 FS21 1 44 State of pin 44 Bit 5 FS1 45 State of pin 45 Bit 4 FS01 1 26 State of pin 26 Bit 3 SPREAD Reserved Bit 2 Reserved Bit 1 Reserved Bit 0
Type R R R R R R R R
0
1
PWD Pin 27
See Frequency Selection Table, Page 1
Off Reserved Reserved Reserved
On
Pin 6 Pin 44 Pin 45 Pin 26 X X X
Notes: 1. These bits reflect the state of the corresponding pins, regardless of whether software programming is enabled or not. SMBus Table: Vendor & Revision ID Register Pin # Name Control Function Byte 4 RID3 Bit 7 RID2 Bit 6 REVISION ID RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VENDOR ID VID1 Bit 1 VID0 Bit 0 SMBus Table: DEVICE ID Pin # Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Type R R R R R R R R
0 -
1 -
PWD X X X X 0 0 0 1
Name DEVID7 DEVID6 DEVID5 DEVID4 DEVID3 DEVID2 DEVID1 DEVID0
Control Function
Device ID = 08 hex
Type R R R R R R R R
0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
1
PWD 0 0 0 0 1 0 0 0
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
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ICS9FG108 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: Byte Count Register Byte 6 Pin # Name BC7 Bit 7 BC6 Bit 6 BC5 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 SMBus Table: Reserved Register Byte 7 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus Table: Reserved Register Pin # Name Byte 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus Table: M/N Programming Enable Pin # Name Byte 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5 M/N_EN OE_Polarity REFOUT_En
Control Function
Writing to this register will configure how many bytes will be read back, default is 07 = 7 bytes.
Type RW RW RW RW RW RW RW RW
0 -
1 -
PWD 0 0 0 0 0 1 1 1
Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Type
0
1
PWD X X X X X X X X
Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Type
0
1
PWD X X X X X X X X
Control Function PLL M/N Programming Enable Select Polarity of OE inputs Enables/Disables REF Reserved Reserved Reserved Reserved Reserved
Type RW RW RW
0 Disable OE# Disable
1 Enable OE Enable
PWD 0 1 1 0 0 0 0 0
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
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ICS9FG108 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: PLL Frequency Control Register Byte 10 Pin # Name Control Function PLL N Div8 N Divider Prog bit 8 Bit 7 PLL N Div9 N Divider Prog bit 9 Bit 6 PLL M Div5 Bit 5 PLL M Div4 Bit 4 M Divider Programming PLL M Div3 Bit 3 bit (5:0) PLL M Div2 Bit 2 PLL M Div1 Bit 1 PLL M Div0 Bit 0 SMBus Table: PLL Frequency Control Register Byte 11 Pin # Name Control Function PLL N Div7 Bit 7 PLL N Div6 Bit 6 PLL N Div5 Bit 5 N Divider Programming PLL N Div4 Bit 4 Byte11 bit(7:0) and Byte10 PLL N Div3 Bit 3 bit(7:6) PLL N Div2 Bit 2 PLL N Div1 Bit 1 PLL N Div0 Bit 0 SMBus Table: PLL Spread Spectrum Control Register Byte 12 Pin # Name Control Function PLL SSP7 Bit 7 PLL SSP6 Bit 6 PLL SSP5 Bit 5 Spread Spectrum PLL SSP4 Bit 4 Programming bit(7:0) PLL SSP3 Bit 3 PLL SSP2 Bit 2 PLL SSP1 Bit 1 PLL SSP0 Bit 0
Type RW RW RW RW RW RW RW RW
0
1
The decimal representation of M and N Divider in Byte 11 and 12 will configure the PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2]
PWD X X X X X X X X
Type RW RW RW RW RW RW RW RW
0
1
The decimal representation of M and N Divider in Byte 11 and 12 will configure the PLL VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2]
PWD X X X X X X X X
Type RW RW RW RW RW RW RW RW
0
1
These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage of PLL
PWD X X X X X X X X
SMBus Table: PLL Spread Spectrum Control Register Pin # Name Control Function Type Byte 13 Reserved Bit 7 PLL SSP14 RW Bit 6 PLL SSP13 RW Bit 5 PLL SSP12 RW Bit 4 Spread Spectrum PLL SSP11 RW Bit 3 Programming bit(14:8) PLL SSP10 RW Bit 2 PLL SSP9 RW Bit 1 PLL SSP8 RW Bit 0
0
1
These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage of PLL
PWD 0 X X X X X X X
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
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ICS9FG108 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: Reserved Test Register Pin # Name Control Function Type 0 1 Byte 14 Bit 7 Bit 6 Bit 5 Reserved Test Register. Do not write to this register, erratic device operation may Bit 4 occur. Bit 3 Bit 2 Bit 1 Bit 0
PWD 1 0 0 0 0 0 0 0
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
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ICS9FG108 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
DIF_STOP# - Assertion (transition from '1' to '0')
Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True = HIGH and DIF_Complement = LOW. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '1', DIFoutputs will be tri-stated.
DIF_STOP# DIF DIF#
DIF_STOP# - De-assertion (transition from '0' to '1')
With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of interest is programmed to '1', then the stopped DIF outputs will be driven High within 15nS of DIF_Stop# de-assertion to a voltage greater than 200mV.
DIF_Stop# DIF DIF#
DIF Internal
Tdrive_DIF_Stop, 15nS >200mV
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
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ICS9FG108 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Absolute Max
Symbol VDD_A VDD_In Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min GND - 0.5 -65 0 Max V DD + 0.5V V DD + 0.5V 150 70 115 Units V V
C C C V
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL VIH VIL IIH IIL1 Input Low Current IIL2 CONDITIONS 3.3 V +/-5% 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pullup resistors VIN = 0 V; Inputs with pull-up resistors Full Active, CL = Full load; f = 400 MHz Full Active, CL = Full load; f = 100 MHz All outputs stopped driven All outputs stopped Hi-Z VDD = 3.3 V Logic Inputs Output pin capacitance From VDD Power-Up and after input clock stabilization to 1st clock Triangular Modulation DIF output enable after DIF_Stop# de-assertion 20% to 80% of VDD MIN 2
VSS 0.3
TYP
MAX
VDD + 0.3
UNITS NOTES V V uA uA uA
0.8 5
-5 -5 -200 215 180 180 51 14 1.5
250 200 200 60 25 7 5 6 1.8 33
mA mA mA mA MHz nH pF pF ms kHz ns ns
1 1 1 1 3 1 1 1 1,2 1 1 1
IDD3.3OP Operating Supply Current IDD3.3STOP Input Frequency 3 Pin Inductance1 Input/Output Capacitance1 Clk Stabilization1,2 Modulation Frequency DIF output enable Input Rise and Fall times
1 2
Fi Lpin CIN COUT TSTAB fMOD tDIFOE tR/t F
1 30 9.8
15 5
Guaranteed by design and characterization, not 100% tested in production. See timing diagrams for timing requirements. 3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to meet
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA ICS9FG108 REV G 04/06/07
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ICS9FG108 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo
1
CONDITIONS VO = Vx Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Crossing variation over all edges see Tperiod min-max values 400MHz nominal 400MHz spread 333.33MHz nominal 333.33MHz spread 266.66MHz nominal 266.66MHz spread 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V
MIN 3000 660 -150 -300 250
TYP
MAX
UNITS
NOTES 1 1
VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm
850 mV 150 1150 550 140 mV mV mV ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps % ps
1 1 1 1 1 1,2,5 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 2 2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 1 1 4 4 1
Average period
Tperiod
Absolute min period
Tabsmin
Measured Differentially 45 VT = 50% 22MHz/1.5MHz/1.5MHz/10ns, tjPCI-ephase14 42 ps Jitter, PCI-e SRC phase 14.31818 MHz REF Clock 22MHz/1.5MHz/1.5MHz/10ns, tjPCI-ephase25 39 ps Jitter, PCI-e SRC phase 25 MHz REF Clock Measurement from differential tjcyc-cyc 40 50 ps Jitter, Cycle to cycle wavefrom 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz or 25 MHz
3 4
Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle Skew, output to output
tr tf d-tr d-tf dt3 tsk3
-300 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.8735 5.8732 7.3728 9.8720 175 175
300 2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 5.4000 10.0030 10.0533
700 700 125 125 55 65
Figures are for down spread. This figure is the peak-to-peak phase jitter as defined by PCI-SIG for a PCI Express reference clock. Please visit http://www.pcisig.com for additional details 5 +/- 150 ppm for 100 MHz outputs
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA ICS9FG108 REV G 04/06/07
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ICS9FG108 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Electrical Characteristics - REF-14.318/25 MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -300 0 300 ppm 1 14.318MHz output nominal 69.8270 69.8413 69.8550 ns 1,2 Clock period Tperiod 25.000MHz output nominal 39.9880 40.0000 40.0120 ns 1,2 Clock period Tperiod I OH = -1 mA 2.4 V 1 Output High Voltage VOH Output Low Voltage V OL IOL = 1 mA 0.4 V 1 V OH @MIN = 1.0 V, -29 -23 mA 1 Output High Current IOH VOH@MAX = 3.135 V VOL @MIN = 1.95 V, Output Low Current IOL 29 27 mA 1 V OL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V 1 1.6 2 ns 1 Rise Time tr1 VOH = 2.4 V, VOL = 0.4 V 1 1.6 2 ns 1 Fall Time tf1 Duty Cycle Jitter
1 2
dt1 tjcyc-cyc
V T = 1.5 V V T = 1.5 V
45 350
55 500
% ps
1 1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818 or 25.00 MHz
Electrical Characteristics - Phase Jitter (Applies to: Revision D Devices, Revision ID = 3)
PARAMETER SYMBOL CONDITIONS
PCIe Gen 1 specs (1.5 - 22 MHz) FBD specs (11-33 MHz) PCIe Gen 2 specs (5-16 MHz, 8-16 MHz)
MIN
TYP
40
MAX
108 3
UNITS Notes
ps ps rms ps rms 1 1 1, 2
Jitter, Phase
tjphasePLL
2.23
3.1
Notes on Phase Jitter:
1
Applicable to all DIF outputs. See http://www.pcisig.com for complete specs. Guaranteed by design and characterization, not tested in production. 2 Specification applies to revision D and later devices.
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
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ICS9FG108 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
DIF Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, Route as non-coupled 50 ohm trace. 0.5 max L2 length, Route as non-coupled 50 ohm trace. 0.2 max L3 length, Route as non-coupled 50 ohm trace. 0.2 max Rs 33 Rt 49.9 Down Device Differential Routing L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Differential Routing to PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max
Unit inch inch inch ohm ohm Unit inch inch Unit inch inch
Figure 1 1 1 1 1 Figure 1 1 Figure 2 2
Figure 1 Down device routing.
L1 Rs L1' Rs HSCL Output Buffer
L2 L2 Rt L3' Rt L3
L4 L4'
PCI Ex Board Down Device REF_CLK Input
Figure 1
Figure 2 PCI Express Connector Routing.
L1 L1'
Rs
L2 L2'
L4 L4' Rt L3' Rt L3 PCI Ex Add In Board REF_CLK Input
Rs HSCL Output Buffer
Figure 2
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
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ICS9FG108 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Alternative termination for LVDS and other common differential signals. Figure 3.
Vdiff Vp-p 0.45 v 0.22v 0.58 0.28 0.80 0.40 0.60 0.3 R1a = R1b = R1 Figure_3. Vcm 1.08 0.6 0.6 1.2 R1 33 33 33 33 R2 150 78.7 78.7 174 R3 100 137 none 140 R4 100 100 100 100 Note
ICS874003i-02 input compatible Standard LVDS
L1 L1'
R1a
L2 L2'
R3
L4 L4'
R4
R1b HSCL Output Buffer
R2a L3'
R2b L3 Down Device REF_CLK Input
R2a = R2b = R2
Cable connected AC coupled application, figure 4
Component R5a,R5b R6a,R6b Cc Vcm Value 8.2K 5% 1K 5% 0.1 uF 0.350 volts Note
3.3 Volts
R5a L4 L4'
Cc Cc
R5b
R6a
R6b PCIe Device REF_CLK Input
Figure_4.
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
16
ICS9FG108 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
48-Lead 300 mil SSOP
N
c
SYMBOL
L
E1 INDEX AREA
E
12 h x 45 D
A A1
A A1 b c D E E1 e h L N VARIATIONS
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
D mm. MIN 15.75 MAX 16.00 MIN .620
D (inch) MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS9FG108YFLF-T
Example:
ICS XXXX y F - LF T
Designation for tape and reel packaging RoHS Compliant (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) Prefix ICS
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
17
ICS9FG108 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
N
c
48-Lead, 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil)
L
(20 mil) In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .011 .0035 .008 SEE VARIATIONS 0.319 BASIC .236 .244 0.020 BASIC .018 .030 SEE VARIATIONS 0 8 -.004
SYMBOL A A1 A2 b c D E E1 e L N aaa VARIATIONS N 48
INDEX AREA
E1
E
12 D
a
A2 A1
A
In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.17 0.27 0.09 0.20 SEE VARIATIONS 8.10 BASIC 6.00 6.20 0.50 BASIC 0.45 0.75 SEE VARIATIONS 0 8 -0.10
-Ce
b SEATING PLANE
D mm. MIN 12.40 MAX 12.60 MIN .488
D (inch) MAX .496
aaa C
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
Ordering Information
ICS9FG108yGLF-T
Example:
ICS XXXX y G - LF T
Designation for tape and reel packaging RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) Prefix ICS
IDTTM/ICSTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG108
REV G 04/06/07
18
ICS9FG108 Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Revision History
Rev. C D E F G Issue Date Description 1. Updated SMBus Byte 0 Bit 6 and 4. 6/1/2005 2. Updated LF Ordering Information to RoHS Compliant. 1. Corrected Pin-Type for Pin 5. 1/13/2006 2. Corrected Revision History Rev. Sequence. 4/13/2006 1. Added +/- 150 ppm accuracy spec for 100 MHz outputs. 4/2/2007 Added Phase Jitter Table 4/6/2007 Updated Pin 26 Description. Page # 9, 15-16 2, 17 1, 6 14 4
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www.IDT.com
For Sales
800-345-7015 408-284-8200 Fax: 408-284-2775
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408-284-6578 pcclockhelp@idt.com
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505
Europe
IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339
TM
(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA
19

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